1. Field of the Invention
Embodiments of the present invention are related to switching regulator control circuits, and, in particular, switching regulator control circuits for driving semiconductor elements, such as light emitting diodes.
2. Description of the Related Art
As is well known in the field of LED (light emitting diode) illumination, current supply devices to supply stable current are required in order to light LED lamps stably. For current supply devices, which need high efficiency and high power factor, generally used are switching regulators of a single stage power factor correction (PFC) type with a PFC converter and a DC-DC converter combined together into a converter structure. This type of switching regulator is controlled with a control IC for example, Type FA5601 control IC manufactured by Fuji Electric Co., Ltd.
For the purpose of reducing a switching loss at turning-on, a discontinuous conduction mode is generally employed, and used is a fixed on-width control, in which an on-width is held constant during the control process, the on-width being the time duration a switching element is in an on-state in each switching period. The Type FA5601 control IC mentioned above, for example, can perform this control.
FIG. 9 shows a construction of a conventional single stage switching regulator (that is, a converter) for fixed on-width control using a quasi-resonant switching process. FIG. 10 shows line voltage Vac waveform and a line current Iac waveform supplied to the input part of the switching regulator shown in FIG. 9. In the switching regulator shown in FIG. 9, the AC power from an AC power source AC is rectified by a diode bridge Db and the obtained line voltage Vac and the line current Iac are fed to the primary winding Lp of a transformer Tra. The secondary current Is induced in the secondary winding Ls of the transformer Tra is rectified and smoothed by a diode D1 (1) and an output capacitor C3 (2) and a resulting DC output voltage Vo is supplied to a load (that is a set of LEDs).
The line voltage Vac shown in FIG. 10 in the input part of the switching regulator of FIG. 9 is represented by the following equation (1).Vac=V1*sin θ  (1)where V1 is a constant and θ is a variable indicating a phase angle in the range of 0 to 180 degrees. The symbol ‘*’ represents multiplication operation.
A power factor PF is usually represented by: power factor PF=effective power Pr/apparent power Pa. The effective power Pr and the apparent power Pa can be given by the following equations (2) and (3).
                    Pr        =                              ∫            0            π                    ⁢                      Vac            *            Iac            *                                                  ⁢                          ⅆ              θ                                                          (        2        )                                Pa        =                                            ∫              0              π                        ⁢                                          Vac                2                            *                                                          ⁢                              ⅆ                θ                            *                                                ∫                  0                  π                                ⁢                                                      Iac                    2                                    *                                                                          ⁢                                      ⅆ                    θ                                                                                                          (        3        )            
During switching operation of the switching element Q1 (11) connected to the primary winding Lp of the transformer Tra shown in FIG. 9, the peak value Idrp of the drain current Idr running through the drain of Q1 is represented byIdrp=Vac*Ton/Lp  (4),where Ton is an on-width and Lp is an inductance of the primary winding of the transformer Tra. Here, it is assumed that the inductance L1 of the low-pass filter (composed of the inductance L1 and capacitors C1 and C2) in the primary side of the transformer Tra and the voltage drop through the switching element Q1 (11) are negligibly small. The peak value Idrp, here, is a peak value of the drain current in one switching period.
Because of the filtering function of the low-pass filter in the primary side of the transformer Tra, a line current Iac is the peak value Idrp of the drain current averaged over the switching periods, and given by the following equation.Iac=½Idrp*D  (5),
where D is a duty factor (or on-duty or simply, a duty).
The duty factor D is given by the equation (6) below and the Idrp is given by the equation (4) above. The secondary current Is induced in the secondary winding Ls of the transformer Tra is represented by the equations (7) and (8) below. In the equation (8), Toff is a time duration in the switching period in which the switching element is in the off-state, or an ‘off-width’ of the switching element.D=Ton/(Ton+Toff)  (6)Is=N*Idrp  (7),
where N is a turn ratio of the transformer.Is=Vo*Toff/Ls  (8)
where Ls is an inductance of the secondary winding and Vo is an output voltage obtained in the secondary side of the transformer Tra.N*N=Lp/Ls  (9)
Transforming the equation (4), the following equation is obtained.Ton=Idrp Lp/Vac  (10)
Using the equations (7) and (8),Toff=Is*Ls/Vo=N*Idrp*Ls/Vo  (11)
Substituting the equations (10) and (11) into the equation (6),
                                                        D              =                                                Ton                  ⁢                                      /                                    ⁢                                      (                                          Ton                      +                      Toff                                        )                                                  =                                                      (                                          Lp                      ⁢                                              /                                            ⁢                      Vac                                        )                                    ⁢                                      /                                    ⁢                                      (                                                                  Lp                        ⁢                                                  /                                                ⁢                        Vac                                            +                                              N                        *                        Ls                        ⁢                                                  /                                                ⁢                        Vo                                                              )                                                                                                                          =                              Lp                *                Vo                ⁢                                  /                                ⁢                                  (                                                            Vo                      *                      Lp                                        +                                          N                      *                      Ls                      *                      Vac                                                        )                                                                                                        =                                                (                                      Lp                    ⁢                                          /                                        ⁢                    Ls                                    )                                *                Vo                ⁢                                  /                                ⁢                                  (                                                                                    (                                                  Lp                          ⁢                                                      /                                                    ⁢                          Ls                                                )                                            *                      Vo                                        +                                          N                      *                      Vac                                                        )                                                                                        (        12        )            Substituting the equation (9) into the equation (12),D=N*N*Vo/(N*N*Vo+N*Vac)=N*Vo/(N*Vo+Vac)  (13)
It is assumed that a resonance period caused by the inductor L1 in the low-pass filter in the primary side of the transformer Tra and the capacitor C4 (12) connected parallel to the switching element Q1 can be ignored. It is also assumed that the voltage drop through the diode D1 (1) in the secondary side of the transformer Tra is negligibly small.
Therefore, the line current Iac is given by the following equation.Iac=½*Vac*Ton/Lp*Vo*N/(Vo*N+Vac)  (14)
Because of the fixed on-width control in this embodiment example, the line current Iac can be given as a function of the line voltage Vac as shown in FIG. 10, and has a nearly sinusoidal waveform. Since the fixed on-width control is assumed, calculation of a power factor PF substituting this expression into the equations (2) and (3) gives a power factor PF value of approximately 1. A calculation taking line voltage dependence into consideration gives generally a power factor PF value in the range of 0.95 to 0.99. If the Vac in the term (Vo*N+Vac) in the equation (14) is neglected, the power factor PF value turns out to be 1.0.
The bottom detection circuit 101 in the control circuit 100 of the switching regulator of FIG. 9 detects a bottom (a minimum) of resonant oscillation current in the primary side of the transformer Tra. The energy stored in the transformer Tra in the on-state of the switching element Q1 (11) is transferred to the secondary side in the off-state of the switching element Q1 (11) until completion of the transfer, at which the resonant oscillation in the primary side begins. The current Is that is proportional to the resonant oscillation current flows to the resistance Rs from the secondary winding Ls, and converted to a voltage on the resistance Rs. This voltage is delivered to the bottom detection circuit 101 that detects a bottom of the delivered voltage to detect the bottom of the resonant oscillation current. An output signal ‘bot’ from the bottom detection circuit 101, indicating arrival ata bottom of the resonant oscillation current, turns to a high level during a short time upon detection of the bottom. When the signal ‘bot’ is delivered through an OR circuit 103 to a one-shot circuit 104, the next switching period begins.
Because a line power is determined by multiplying the line voltage Vac and the line current Iac together, the line power obtained is very small in a low phase region near the phase angle of zero degrees or 180 degrees, and the line power is large in a high phase region. As a result, large oscillation occurs in the line power, causing a substantial ripple of output current Io. To suppress this ripple within a certain limit, an electrolytic output capacitor C3 (2) of a large capacitance is required. For example, the LED lamp specification of 21 V/350 mA needs a capacitance of the C3 (2) of 500 to 1,000 μF.
Because a power supply board for an LED lamp is contained in the LED lamp, the size of the output electrolytic capacitor is an obstacle against downsizing of an LED system. Consequently, the capacitance of the capacitor C3 (2) must be reduced. This needs suppressing oscillation of the line power. For this purpose, a fixed peak current control scheme is employed in which the peak value Idrp of the drain current is kept constant. The control IC FA 5601 mentioned previously, for example, can fit to the fixed peak current control scheme.
FIG. 11 shows a construction of a conventional single stage, power factor correction type switching regulator (that is a converter) for a fixed peak current control scheme employing quasi-resonant switching method. The line current Iac in this case is represented as follows using the equations (5) and (13).Iac=½*Idrp*Vo*N/(Vo*N+Vac)  (15)
The line current Iac is nearly in inverse proportion to the line voltage Vac in the input part of the switching regulator, and has an approximately inverse sinusoidal waveform as shown in FIG. 12. The fixed peak current control scheme used in the switching regulator of FIG. 11 greatly suppresses the oscillation in the line power and reduces the capacitance of the output electrolytic capacitor C3 (2) to about a half. A power factor, however, deteriorates to about 0.6. Although a design to achieve a power factor PF of about 0.9 is possible by introducing a maximum on-width control scheme, the design involves a problem of great dependency on the input voltage. For example, the design that provides a power factor PF of 0.87 owing to adjustment by the maximum on-width control in the case of an input line voltage Vac of 100 Vrms results in a power factor PF of 0.67 in the case of an input line voltage Vac of 230 Vrms.
The output signal ‘bot’ from the bottom detection circuit 201 in the control circuit 200 of the switching regulator of FIG. 11, indicating, like the signal ‘bot’ in FIG. 9, arrival at a bottom of the resonant oscillation current, turns to a high level during a short time upon detection of the bottom. When the signal ‘bot’ is delivered through an OR circuit 203 to a one-shot circuit 204, the next switching period begins.
Japanese Unexamined Patent Application Publication No. 2007-080771 (also referred to herein as “Patent Document 1”) discloses a circuit to control the current running in LEDs constant. Japanese Unexamined Patent Application Publication No. 2002-352980 (also referred to herein as “Patent Document 2”) discloses a circuit to control the current running in a mercury lamp to equalize always to the rated current. Both the Patent Documents 1 and 2 disclose a technology falling into the fixed peak current control scheme mentioned previously in which the peak current Idrp is controlled constant.